Manas Ranjan Tripathy
Assistant Professor II
Dr. Manas Ranjan Tripathy has more than 16 years of experience in teaching and research. He started his academic career as a lecturer in the Department of Instrumentation and Electronics Engineering, OUTR, Bhubaneswar (Formerly known as CET, Bhubaneswar) in the year 2008. Later, he joined SOA University, Bhubaneswar in 2010. He earned his PhD from the Indian Institute of Technology, Banaras Hindu University, Varanasi in 2020. Before joining KIIT University, he worked as an Assistant Professor there at SRM University, AP. Dr Manas has authored and co-authored 40 research articles in various peer-reviewed journals and conference proceedings including 3 papers in IEEE Transactions and one Nature Indexed journal. He was invited by many institutions to deliver talks related to the VLSI domain. Dr. Manas has also received best paper awards at IEEE Conferences. He also served as a reviewer in many international journals and conferences. Dr. Manas Ranjan Tripathy, Assistant Professor-II in the School of Electronics Engineering, KIIT Deemed to be University has participated in many INUP programs held at IISc, Bangalore related to the fabrication and characterization of nanoscale devices.
Profile Links
Email :
[email protected]
Scopus Id :
https://www.scopus.com/authid/detail.uri?authorId=38962197800
Social Links
PhD, IIT BHU, Varanasi
Research Interests
Modelling and Simulation of Advanced Field Effect Transistors, Memristor Modeling and its Circuit Level Applications, Neuromorphic Computing and Neuromorphic Chip Design, Advance Photovoltaic Devices, AI and ML
Projects
Submitted (SPARC), IIT Kharagpur
Administrative Responsibility
1. IEEE Conference Coordinator in SOA University, Bhubaneswar 2. FDP Coordinator/Convener in SRM University, AP 3. Faculty Advisor for Outdoor Game Club in SRM University, AP
Awards & Honours
1. Best Paper award in IEEE CONECCT 2020, IEEE Bengaluru Section 2. University Gold Medal in MTech (Microelectronics), SOA University, Bhubaneswar
Memberships
IEEE
1. Manas Ranjan Tripathy, Ashish Kumar Singh, A Samad, Sweta Chander, Kamalaksha Baral, Prince Kumar Singh, and Satyabrata Jit, ‘Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications’, IEEE Transactions on Electron Devices, vol 67, no 3, pp 1285-92,2020. DOI: 10.1109/TED.2020.2964428
2. Manas Ranjan Tripathy, and Satyabrata Jit, “Lateral and Vertical Gate Oxide Stacking Impact on Noise Margins and Delays for the 8T SRAM Designed with Source Pocket Engineered GaSb/Si Heterojunction Vertical TFET: A Reliability Study,” IEEE Transactions on Device and Materials Reliability, vol 21, no 3, pp. 372-378, September 2021. DOI: 10.1109/TDMR.2021.3098437
3. Manas Ranjan Tripathy, A Samad, Ashish Kumar Singh, Prince Kumar Singh, Kamalaksha Baral, Ashwini Kumar Mishra, and Satyabrata Jit, “Impact of Interface Trap Charges on Electrical Performance Characteristics of a Source Pocket Engineered Ge/Si
4. Manas Ranjan Tripathy, Ashish Kumar Singh, A Samad, Sweta Chander, Kamalaksha Baral, Prince Kumar Singh, and Satyabrata Jit, “ III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications,” Superlattices and Microstructures, vol. 142, 2020, 106494. doi:10.1016/j.spmi.2020.106494
5. Manas Ranjan Tripathy, Ashish Kumar Singh, A Samad, Prince Kumar Singh, Kamalaksha Baral, and Satyabrata Jit, “Impact of Heterogeneous Gate Dielectric on DC, RF and Circuit-Level Performance of Source-Pocket Engineered Ge/Si Heterojunction Vertical TFET”, Semiconductor Science and Technology, vol. 35, 105014, 2020, DOI: 10.1088/1361-6641/aba418
6. Ashish Kumar Singh, Manas Ranjan Tripathy, Kamalaksha Baral, and Satyabrata Jit, “GaSb/GaAs Type-II Heterojunction TFET on SELBOX Substrate for Dielectric Modulated Label-Free Biosensing Application”, IEEE Transactions on Electron Devices, vol. 69, no. 9, pp. 5185-5192, 2022. doi:10.1109/TED.2022.3191295
7. Zohming liana, Manas Ranjan Tripathy, Bijit Choudhuri, Brinda Bhowmick, “Device and circuit-level performance evaluation of DG-GNR-DMG vertical tunnel FET”, Micro and Nanostructures, Vol. 194, 2024, 207942, doi: 10.1016/j.micrna.2024.207942.
8. Kamalaksha Baral, Prince Kumar Singh, Gautam Kumar, Ashish Kumar Singh, Manas Ranjan Tripathy, Sanjay Kumar, and Satyabrata Jit, “Impact of ion implantation on stacked oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and circuit level analysis”, Materials Science in Semiconductor Processing, Volume 133, 2021, 105966, DOI: 10.1016/j.mssp.2021.105966
9. Ashwini Kumar Mishra, Deepak Kumar Jarwal, Bratindranath Mukherjee, Amit Kumar, Smrity Ratan, Manas Ranjan Tripathy, and Satyabrata Jit, “Au nanoparticles modified CuO nanowire electrode based non-enzymatic glucose detection with improved linearity”, Scientific Report, 10, 11451, 2020. https://doi.org/10.1038/s41598-020-67986-4
10. Ashish Kumar Singh, Manas Ranjan Tripathy, Kamalaksha Baral, Prince Kumar Singh, and Satyabrata Jit, “ Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate”, Appl. Phys. A 126, 681, 2020. https://doi.org/10.1007/s00339-020-03869-9