Srinibasa Padhy
Srinibasa Padhy
Assistant Professor
Mr Srinibasa Padhy has been active in teaching the field of Electronics Engg. since the year of 2006.The Teaching and research activities had originated from the dept. of Electronics Engg. from Roland Institute of Technology,Berhampur. The career in research has augmented further after the degree in M Tech from the pioneer institute IIT, Kharagpur in the emerging field of Microelectronics and VLSID from 2011.The stint of teaching and research has captured the momentum since joining in the most sought KIIT university,Bhubaneswar.Now the research is focuses on thin-film fabrication,characterization and solar cell device performance assessment and simulation.
Educational Qualification
M.Tech,PhD(Pursuing)
Research Interests
Microelectronics,VLSI,Solar Devices
Administrative Responsibility
1.FIC School level QA cell,2.Supt. Of Hostel KP-10
Memberships
ISC
M.Tech,PhD(Pursuing)
Research Interests
Microelectronics,VLSI,Solar Devices
Administrative Responsibility
1.FIC School level QA cell,2.Supt. Of Hostel KP-10
Memberships
ISC
Journals/Conferences :
1. Vishvas kumar, Srinibasa Padhy,Arindam Basak ,Udai P. Singh” Effect of HCl and NH 4 OH Etching on CZTSSe
Absorber Layer” Vacuum,155, pp. 336-338(2018), scopus indexed and SCI (IF 2.067)
2. Padhy Srinibasa., Kumar, V., Singh, U.P.” CZTSSe absorber layer formation and impact of annealing process
on its properties” Journal of Materials Science: Materials in Electronics,30(2), pp. 1100-1108 (2019) online
available in nov. 23,2018,SCOPUS indexed and SCI (IF 2.324)
3. Pani, B., Padhy, S., Singh, U.P.” A Comparative study of kesterite thin films prepared from different ball milled
precursors Volume 4, Issue 14, 2017, Pages 12536-12544 (scopus)
4. S Padhy,s s bal,U P Singh Cu2ZnSn(S,Se)4 absorber layer formation and characterization using solution dip
coating and selenization method https://doi.org/10.1088/2053-1591/ab5df9 (SCIE and SCOPUS) accepted
Conference Publications
A Paper on “Effect of Ge & ZnO inter-layer on the properties of CZTSSe Absorber layer” by Sriya S Bal, Srinibasa Padhy, Udai P Singh presented in ICSEP-19 FROM 19th to 21st Dec-2019 held in KIIT(DU) Bhubaneswar.
A paper on “Variation and Evaluation of CZTS layer parameters for optimum performance: A Simulative Approach” by Rajeshwari Mannu,Srinibasa Padhy,R Prasad,Udai P Singh presented in ICSEP-19 FROM 19th to 21st Dec-2019 held in KIIT(DU) Bhubaneswar
A paper on “Numerical investigation of optimized CZTSSe based solar cell in Wx-Amps environment” by Soumya Priyadarshini Mohanty, Srinibasa Padhy, Joy Chowdhury, and Udai P. Singh presented in International Conference on Inventive Research in Material Science and Technology,AIP Conf. Proc. 1966, 020024-1–020024-6; https://doi.org/10.1063/1.5038703(SCOPUS)
A paper on “Cu2ZnSn(S,Se)4 Absorber Layer using Solution Dip Coating and Selenization” by Srinibasa Padhy, Sriya S Bal, Vishvas Kumar, Udai P Singh presented in (M-TECS 2018 BARC,Mumbai September 26-29,2018
A Paper on “Impact of annealing temparature profile on the formation of cztsse absorber layer ” by Srinibasa Padhy, Vishvas Kumar, S.Bhattacharya, Udai P Singh presented in PVSEC 27,OSTLOW,JAPAN to be held on Nov 12 2017
A paper on” Effect of HCl and NH4OH Etching on CZTSSe Absorber Layer” by Vishvas kumar, Srinibasa Padhy,Arindam Basak ,Udai P. Singh presenteded in ICTF-2017,New Delhi to be held from nov.13-17
A paper on “A Comparative study of kesterite thin films prepared from different ball milled precursors “ by Bhagyashree Pani, Srinibasa Padhy and Udai P Singh presented in ICSEP-2016 ,18th to 20th Dec 2016 in KIIT
A Paper on “A review on CZTS based solar cell” by Srinibasa padhy and U P Singh presented in the conference frontiers in materials research and application(FMRA) held on oct. 27-28,2016,ferozepur,punjab
A paper on “Design of Low Power Robust Symmetric SRAM Cell Using Gated Ground Technique”by T Roy and Srinibasa Padhy in International Journal of Industrial Electronics and Electrical Engineering(IJIEEE) 2015
A paper on” Enhanced robust architecture of single bit sram cell using drowsy cache and super cutoff cmos concept” by R Choudhury,Srinibasa Padhy and N k Rout in 24th IRF International conference 2015.
A paper on”Modified Double edge triggered clock Branch sharing architecture for ultra low power design” by Komal Priyadarshini, Srinibasa Padhy presented in International Journal of Computer Applications (0975 – 8887) from International Conference on Microelectronics, Circuits and Systems (MICRO-2014)
A paper on “Low power high speed 64 bit sram architecture using sccmos and drowsy cache concept” by Geeta Pattnaik, Srinibasa Padhy presented in Conference on Microelectronics, Circuits and Systems (MICRO-2014) ISBN no: 81-8524-46-0
A paper on “A Technique for Impedance Matching in design of low noise amplifier for Zigbee receiver frontend” by S Mohanty and Srinibasa Padhy presented in Conference on Microelectronics, Circuits and Systems (MICRO-2014 ISBN no: 81-8524-46-0
1. Vishvas kumar, Srinibasa Padhy,Arindam Basak ,Udai P. Singh” Effect of HCl and NH 4 OH Etching on CZTSSe
Absorber Layer” Vacuum,155, pp. 336-338(2018), scopus indexed and SCI (IF 2.067)
2. Padhy Srinibasa., Kumar, V., Singh, U.P.” CZTSSe absorber layer formation and impact of annealing process
on its properties” Journal of Materials Science: Materials in Electronics,30(2), pp. 1100-1108 (2019) online
available in nov. 23,2018,SCOPUS indexed and SCI (IF 2.324)
3. Pani, B., Padhy, S., Singh, U.P.” A Comparative study of kesterite thin films prepared from different ball milled
precursors Volume 4, Issue 14, 2017, Pages 12536-12544 (scopus)
4. S Padhy,s s bal,U P Singh Cu2ZnSn(S,Se)4 absorber layer formation and characterization using solution dip
coating and selenization method https://doi.org/10.1088/2053-1591/ab5df9 (SCIE and SCOPUS) accepted
Conference Publications
A Paper on “Effect of Ge & ZnO inter-layer on the properties of CZTSSe Absorber layer” by Sriya S Bal, Srinibasa Padhy, Udai P Singh presented in ICSEP-19 FROM 19th to 21st Dec-2019 held in KIIT(DU) Bhubaneswar.
A paper on “Variation and Evaluation of CZTS layer parameters for optimum performance: A Simulative Approach” by Rajeshwari Mannu,Srinibasa Padhy,R Prasad,Udai P Singh presented in ICSEP-19 FROM 19th to 21st Dec-2019 held in KIIT(DU) Bhubaneswar
A paper on “Numerical investigation of optimized CZTSSe based solar cell in Wx-Amps environment” by Soumya Priyadarshini Mohanty, Srinibasa Padhy, Joy Chowdhury, and Udai P. Singh presented in International Conference on Inventive Research in Material Science and Technology,AIP Conf. Proc. 1966, 020024-1–020024-6; https://doi.org/10.1063/1.5038703(SCOPUS)
A paper on “Cu2ZnSn(S,Se)4 Absorber Layer using Solution Dip Coating and Selenization” by Srinibasa Padhy, Sriya S Bal, Vishvas Kumar, Udai P Singh presented in (M-TECS 2018 BARC,Mumbai September 26-29,2018
A Paper on “Impact of annealing temparature profile on the formation of cztsse absorber layer ” by Srinibasa Padhy, Vishvas Kumar, S.Bhattacharya, Udai P Singh presented in PVSEC 27,OSTLOW,JAPAN to be held on Nov 12 2017
A paper on” Effect of HCl and NH4OH Etching on CZTSSe Absorber Layer” by Vishvas kumar, Srinibasa Padhy,Arindam Basak ,Udai P. Singh presenteded in ICTF-2017,New Delhi to be held from nov.13-17
A paper on “A Comparative study of kesterite thin films prepared from different ball milled precursors “ by Bhagyashree Pani, Srinibasa Padhy and Udai P Singh presented in ICSEP-2016 ,18th to 20th Dec 2016 in KIIT
A Paper on “A review on CZTS based solar cell” by Srinibasa padhy and U P Singh presented in the conference frontiers in materials research and application(FMRA) held on oct. 27-28,2016,ferozepur,punjab
A paper on “Design of Low Power Robust Symmetric SRAM Cell Using Gated Ground Technique”by T Roy and Srinibasa Padhy in International Journal of Industrial Electronics and Electrical Engineering(IJIEEE) 2015
A paper on” Enhanced robust architecture of single bit sram cell using drowsy cache and super cutoff cmos concept” by R Choudhury,Srinibasa Padhy and N k Rout in 24th IRF International conference 2015.
A paper on”Modified Double edge triggered clock Branch sharing architecture for ultra low power design” by Komal Priyadarshini, Srinibasa Padhy presented in International Journal of Computer Applications (0975 – 8887) from International Conference on Microelectronics, Circuits and Systems (MICRO-2014)
A paper on “Low power high speed 64 bit sram architecture using sccmos and drowsy cache concept” by Geeta Pattnaik, Srinibasa Padhy presented in Conference on Microelectronics, Circuits and Systems (MICRO-2014) ISBN no: 81-8524-46-0
A paper on “A Technique for Impedance Matching in design of low noise amplifier for Zigbee receiver frontend” by S Mohanty and Srinibasa Padhy presented in Conference on Microelectronics, Circuits and Systems (MICRO-2014 ISBN no: 81-8524-46-0