Pradipta Dutta
Pradipta Dutta
Associate Professor
Pradipta Dutta is having 13+ Years of Teaching and Research experience. He is currently doing research in the domain of MOS Device Physics,III-V Heterostructure Devices ,Thin Film Related Devices and Quantum Transport in Low Dimensional Systems . He is a Life Member of Indian Society for Technical Education, New Delhi, India. He is also a member of Indian Science Congress.
Profile Links
Email :
[email protected]
Scopus Id :
36600330800
Google Scholar :
https://scholar.google.com/citations?hl=en&user=y_l5UV4AAAAJ&view_op=list_works&sortby=pubdate
Social Links
Educational Qualification
Ph,D
Research Interests
Simulation and modeling of Nano scaled devices.
Administrative Responsibility
Assistant Exam Controller
Memberships
Life Member of Indian Society for Technical Education, New Delhi, India. Indian Science Congress.
Ph,D
Research Interests
Simulation and modeling of Nano scaled devices.
Administrative Responsibility
Assistant Exam Controller
Memberships
Life Member of Indian Society for Technical Education, New Delhi, India. Indian Science Congress.
Journals/Conferences :
A. Journal Papers:
i. P. Dutta, B. Syamal, A. Dutta, K. Kalyan and C. K. Sarkar "Short Channel Drain Current Model for Asymmetric Heavily / Lightly Doped DG MOSFETs" Pramana - J Phys (2017) 89:33.
ii. P. Dutta, K. Koley, A. Dutta and C. K. Sarkar, "An Analytical BTBT Current Model of Symmetric/Asymmetric 4T Tunnel Double Gate FETs With Ambipolar Characteristic," in IEEE Transactions on Electron Devices, vol. 63, no. 7, pp. 2700-2707, July 2016.
iii. P. Dutta, B. Syamal, K. Kalyan, N. Mohankumar and C.K. Sarkar, “A New Threshold Voltage and Drain Current Model for Lightly / Heavily Doped Surrounding Gate MOSFETs”, Journal of Computational and Theoretical Nanoscience, Volume 12, Number 9, September 2015, pp. 2515-2522(8).
iv. P. Dutta, B. Syamal, N. Mohankumar and C. K. Sarkar, “A 2-D surface-potential-based threshold voltage model for short channel asymmetric heavily doped DG MOSFETs” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Volume 27, Issue 4, 17 January 2014, Pages 682-690.
v. P. Dutta, B. Syamal, N. Mohankumar and C. K. Sarkar, “A surface potential based drain current model for asymmetric double gate MOSFETs”, Solid-State Electronics, Volume 56, Issue 1, February 2011, Pages 148-154.
B. Conference Papers
i. P. Dutta, S.Mohanty, and J.K.Das, "Simulation Study of Junctionless Double Gate Tunnel Field Effect Transistor in 20nm Channel Length." Accepted in “2018 International Conference on Applied Electromagnetics, Signal Processing and Communication (AESPC)”
ii. P. Dutta, R.Mohapatra, "Improvement of Trans Conductance in double channel AlGaN/GaN HEMT." Accepted in “2018 International Conference on Applied Electromagnetics, Signal Processing and Communication (AESPC)”
iii. P. Dutta, S. P. Nayak, S. K. Mohapatra, "Suppressing the issues of current collapse and high on-resistance in Al0.3Ga0.7N/GaNHEMT to provide better switching functionality of inverter through MOSHEMT." 2017, 1st international conference on Electronics, Materials and Engineering and Nano-Technology (IEMENTech).
iv. P. Dutta, S. P. Nayak, and S. K. Mohapatra, "Improvement of transconductance and gate source capacitance of Al0.27Ga0.73N/GaN HEMT at 45nm gate length with In0.1Ga0.9N back-barrier," 2017 Devices for Integrated Circuit (DevIC), Kalyani, 2017, pp. 131-135.
v. P. Dutta and S. J. Medisetty, "Performance analysis of junctionless double gate MOSFET using Silicon and In0.53Ga0.47As," 2016 International Conference on Communication and Signal Processing (ICCSP), Melmaruvathur, 2016, pp. 0991-0995.
vi. P. Dutta and R.R.Biswal, “A Comparative Study of Back Gate Misalignment Effects for Nano Szcale Symmetric and Asymmetric Double Gate MOSFETS”, International Journal of Advanced Engineering and Nano Technology, Volume 2, Issue 6, May 2015, Pages 37- 42.
vii. P. Dutta and A. Chavan, “Energy Efficient optimum path selection algorithm for WSN Communication”, National Conference on VLSI and Signal Processing: NCVSP -11 held on 30th June and 1st July 2011.
viii. P. Dutta, B. Syamal, N. Mohankumar and C. K. Sarkar, “ Unified drain current model for independently driven double gate MOSFETs”, Microelectronics (ICM), 2010 International Conference on 19-22 Dec. 2010, Pages 44 – 47.
ix. P. Dutta and P. Pallavi, "Muti-Carrier CDMA overview with BPSK modulation in Rayleigh channel", Computer Science and Information Technology (ICCSIT), 2010 3rd IEEE International Conference on, Chengdu, 2010, pp. 464-469.
A. Journal Papers:
i. P. Dutta, B. Syamal, A. Dutta, K. Kalyan and C. K. Sarkar "Short Channel Drain Current Model for Asymmetric Heavily / Lightly Doped DG MOSFETs" Pramana - J Phys (2017) 89:33.
ii. P. Dutta, K. Koley, A. Dutta and C. K. Sarkar, "An Analytical BTBT Current Model of Symmetric/Asymmetric 4T Tunnel Double Gate FETs With Ambipolar Characteristic," in IEEE Transactions on Electron Devices, vol. 63, no. 7, pp. 2700-2707, July 2016.
iii. P. Dutta, B. Syamal, K. Kalyan, N. Mohankumar and C.K. Sarkar, “A New Threshold Voltage and Drain Current Model for Lightly / Heavily Doped Surrounding Gate MOSFETs”, Journal of Computational and Theoretical Nanoscience, Volume 12, Number 9, September 2015, pp. 2515-2522(8).
iv. P. Dutta, B. Syamal, N. Mohankumar and C. K. Sarkar, “A 2-D surface-potential-based threshold voltage model for short channel asymmetric heavily doped DG MOSFETs” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Volume 27, Issue 4, 17 January 2014, Pages 682-690.
v. P. Dutta, B. Syamal, N. Mohankumar and C. K. Sarkar, “A surface potential based drain current model for asymmetric double gate MOSFETs”, Solid-State Electronics, Volume 56, Issue 1, February 2011, Pages 148-154.
B. Conference Papers
i. P. Dutta, S.Mohanty, and J.K.Das, "Simulation Study of Junctionless Double Gate Tunnel Field Effect Transistor in 20nm Channel Length." Accepted in “2018 International Conference on Applied Electromagnetics, Signal Processing and Communication (AESPC)”
ii. P. Dutta, R.Mohapatra, "Improvement of Trans Conductance in double channel AlGaN/GaN HEMT." Accepted in “2018 International Conference on Applied Electromagnetics, Signal Processing and Communication (AESPC)”
iii. P. Dutta, S. P. Nayak, S. K. Mohapatra, "Suppressing the issues of current collapse and high on-resistance in Al0.3Ga0.7N/GaNHEMT to provide better switching functionality of inverter through MOSHEMT." 2017, 1st international conference on Electronics, Materials and Engineering and Nano-Technology (IEMENTech).
iv. P. Dutta, S. P. Nayak, and S. K. Mohapatra, "Improvement of transconductance and gate source capacitance of Al0.27Ga0.73N/GaN HEMT at 45nm gate length with In0.1Ga0.9N back-barrier," 2017 Devices for Integrated Circuit (DevIC), Kalyani, 2017, pp. 131-135.
v. P. Dutta and S. J. Medisetty, "Performance analysis of junctionless double gate MOSFET using Silicon and In0.53Ga0.47As," 2016 International Conference on Communication and Signal Processing (ICCSP), Melmaruvathur, 2016, pp. 0991-0995.
vi. P. Dutta and R.R.Biswal, “A Comparative Study of Back Gate Misalignment Effects for Nano Szcale Symmetric and Asymmetric Double Gate MOSFETS”, International Journal of Advanced Engineering and Nano Technology, Volume 2, Issue 6, May 2015, Pages 37- 42.
vii. P. Dutta and A. Chavan, “Energy Efficient optimum path selection algorithm for WSN Communication”, National Conference on VLSI and Signal Processing: NCVSP -11 held on 30th June and 1st July 2011.
viii. P. Dutta, B. Syamal, N. Mohankumar and C. K. Sarkar, “ Unified drain current model for independently driven double gate MOSFETs”, Microelectronics (ICM), 2010 International Conference on 19-22 Dec. 2010, Pages 44 – 47.
ix. P. Dutta and P. Pallavi, "Muti-Carrier CDMA overview with BPSK modulation in Rayleigh channel", Computer Science and Information Technology (ICCSIT), 2010 3rd IEEE International Conference on, Chengdu, 2010, pp. 464-469.