B Shivalal Patro

Assistant Professor

B. Shivalal Patro is having 7+ years of teaching and 8+ years of research experience. He is currently doing research in macro modeling and synthesis of analog circuits using machine learning and optimization techniques.

Profile Links

Email :
[email protected]
Scopus Id :
55576057200
Google Scholar :
https://scholar.google.com/citations?user=jl9HAJEAAAAJ&hl=en&oi=ao

Social Links

Educational Qualification
Mtech, PhD

Research Interests
VLSI, MACHINE LEARNING

Memberships
IEEE , Lifetime member of ISC
Journals/Conferences :
Vandana, B., Parashar, P., Patro, B. S., Pradhan, K. P., Mohapatra, S. K., & Das, J. K. (2019). Mole Fraction Dependency Electrical Performances of Extremely Thin SiGe on Insulator Junctionless Channel Transistor (SG-OI JLCT). In Advances in Signal Processing and Communication (pp. 573–581). Springer,2019.

Patro, B. S., & Ray, K. B. (2018). Leakage Power Minimization in ST-SRAM Cell Using Adaptive Reverse Body Bias Technique. International Journal of Computer Science and Mobile Applications, 6(4), 196-204.

Vandana, B., Patro, B. S., Das, J. K., Kaushik, B. K., & Mohapatra, S. K. (2018). Inverted 'T'Junctionless FinFET (ITJL FinFET): Performance Estimation through Device Geometry Variation. ECS Journal of Solid State Science and Technology, 7(4), Q52--Q59.

Vandana, B., Mohapatra, S. K., Das, J. K., & Patro, B. S. (2017). Prospects of 2D Junctionless Channel Transistor (JLCT) Towards Analog and RF Metrics Using Si and SiGe in Device Layer. Journal of Low Power Electronics, 13(3), 536–544.
Panigrahi, J. K., Patro, B. S., & Patnaik, D. (2017). A 16.4 GHz, 2.9 μW CMOS Voltage-Controlled Ring Oscillator in 45 nm. IUP Journal of Telecommunications, 9(3).

Patro, S., & Mandal, S. K. (2017). A Multi Output Formulation for Analog Circuits Using MOM-SVM. Indonesian Journal of Electrical Engineering and Computer Science, 7(1), 90–96.

Vandana, B., Patro, B. S., Das, J. K., & Mohapatra, S. K. (2017). Physical insight of junctionless transistor with simulation study of Strained channel. ECTI Transactions on Electrical Engineering, Electronics, and Communications, 15(1), 1–7.

Padhy, S., Patro, B. S., Swain, M., & Das J K. (2017). A Unified Ultra-Low Power Architecture of Probabilistic Adder Based on GDI Technique, Journal of VLSI Design Tools & Technology, 6(3), 45-55 .

Vandana, B., Das, J. K., Patro, B. S., & Mohapatra, S. K. (2017). Exploration towards Electrostatic Integrity for SiGe on Insulator (SG-OI) on Junctionless Channel transistor (JLCT). Facta Universitatis, Series: Electronics and Energetics, 30(3), 383–390.

Patro, B. S., Biswas, S., Roy, I., & Vandana, B. (2017). 1 GHz High Sensitivity Differential Current Comparator for High Speed ADC. Journal of Digital Integrated Circuits in Electrical Devices, 2(1), 7–12.

Patro, S., & Mandal, S. K. (2017). Support Vector Machine Based Macro-Modeling of Voltage Controlled Oscillator for Fast Synthesis Purpose, Journal of Advanced Research in Dynamical and Control Systems, Special Edition, 655-663.

Patro, B. S., & Mandal, S. K. (2017). Macro-modeling of OTA using ANN for fast synthesis. In International Journal of Engineering, Science And Mathematics. 6(Special Issue), 752-759.


Patro, B. S., & Mandal, S. K. (2016). A Novel Modeling Technique for Operational Amplifier Using RBF-ELM. Journal of Engineering Science and Technology Review, 9(4), 74–76.

Tripathy, S., Mandal, S. K., Patro, B. S., & Omprakash, L. B. (2016). Low Power, High Speed 8-Bit Magnitude Comparator in 45nm Technology for Signal Processing Application. Indian Journal of Science and Technology, 9(13).

Ray, K. B., Mandal, S. K., & Patro, S. (2016). Low Power FGSRAM Cell Using Sleepy and LECTOR Technique. Indonesian Journal of Electrical Engineering and Computer Science, 4(2).

Ray, K. B., Mandal, S. K., & Patro, B. S. (2016). Low Power, High speed, Low leakage Floating Gate SRAM Cell using LECTOR Technique. Indian Journal of Science and Technology, 9(45).

Mohapatra, S K., Vandana, B., Patro, B S., & Das, J K. (2016). SiGe on Insulator (SG-OI) on Junctionless Channel Transistor (JLCT): A new device for scaling with improved switching action, 2nd International Conference on Micro-electronics, Communication and Computation-2016, SanDiego, USA, 215-221.

Patro, B S., Vandana, B., & Mandal S K. (2016). A Low Phase Noise Wide Tuning Range CMOS Differential Ring Voltage Controlled Oscillator for Signal Processing, International Conference on Communication, Circuits and Systems, In International Journal of Engineering Research and Technology, 13-15.

Roy, I., Biswas, S., & Patro, B. S. (2015). Low Power High Speed Differential Current Comparator.

Tripathy, S., Omprakash, L. B., Mandal, S. K., & Patro, B. S. (2015). Low power multiplier architectures using vedic mathematics in 45nm technology for high speed computing. In Communication, Information & Computing Technology (ICCICT), 2015 International Conference on (pp. 1–6).

Tripathy, S., Omprakash, L. B., Patro, B. S., & Mandal, S. K. (2014). Low power, high speed full adder architectures in 45nm technology. In International conference on VLSI and signal processing, IIT Kharagpur.

Anand, A., Mandal, S. K., Dash, A., & Patro, B. S. (2013). FGMOS based low-voltage low-power High output impedance regulated Cascode current mirror. International Journal of VLSI Design & Communication Systems, 4(2), 39.

Tripathy, S., Prakash, L., Patro, B. S., & Mandal, S. K. (2013). A comparative analysis of different 8-bit adder topologies at 45 nm technology. International Journal of Engineering Research and Technology, 2(10).

Dash, A., Mandal, S. K., Patro, B. S., & Anand, A. (2013). A low offset fast settling rail-to-rail stable operational amplifier in 180 nm technology. In Information & Communication Technologies (ICT), 2013 IEEE Conference on (pp. 793–797).

Patro, B. S., Panigrahi, J. K., & Mandal, S. K. (2012). A 6--17 GHz linear wide tuning range and low power ring oscillator in 45nm CMOS process for electronic warfare. In Communication, Information & Computing Technology (ICCICT), 2012 International Conference on (pp. 1–4).

Books :

Vandana, B., & Patro, B. S. (2016). Challenges and Limitations of Low Power Techniques: Low Power Methodologies in. Design and Modeling of Low Power VLSI Systems, 48.
Patro, B. S., & Vandana, B. (2016). Low Power Strategies for beyond Moore’s Law Era: Low Power Device Technologies. Design and Modeling of Low Power VLSI Systems, 27.