Jointly organized by IEEE Council on Electronic Design Automation (CEDA) Student branch chapter (SBC) and IEEE Solid-State Circuits Society (SSCS) Student branch chapter (SBC) and School of Electronics Engineering, KIIT (DU), Bhubaneswar, India
Event Details:
Title of the Event: 3 Days TTTC India Workshop on VLSI Testing
Date: 31st October 2025-2nd November 2025
Time: 9:00 AM to 5:00 PM (Friday and Saturday) and 9:00 AM to 2:00 PM (Sunday)
Venue (Physical Location): School of Electronics Engineering, Campus-12, KIIT (DU)
Mode: Google Offline
Number of Participants: 40
Purpose of the Event: Academic knowledge enhancement and social awareness and outreach
Write-up on the Event:
The “3 Days TTTC India Workshop on VLSI Testing,” organized from 31st October 2025 to 2nd November 2025 at the School of Electronics Engineering, KIIT (Deemed to be University), Bhubaneswar, stood as a remarkable initiative aimed at bridging the gap between academic learning and industry practices in the field of semiconductor testing. Jointly organized by the IEEE Solid-State Circuits Society (SSCS) Student Branch Chapter and the IEEE Council on Electronic Design Automation (CEDA) Student Branch Chapter, this workshop reflected a strong commitment towards advancing technical knowledge in VLSI design and testing. Conducted in offline mode with Google-based coordination support, the workshop witnessed the enthusiastic participation of 40 students, creating a highly engaging and collaborative learning environment. The sessions were held from 9:00 AM to 5:00 PM on Friday and Saturday, and from 9:00 AM to 2:00 PM on Sunday, ensuring an intensive and immersive three-day technical experience. The workshop was conducted under the guidance and support of the IEEE Test Technology Technical Community (TTTC), a prestigious body under the IEEE Computer Society known for its significant contributions in the domain of VLSI testing, with active involvement from industry veterans. A major highlight of the workshop was its comprehensive coverage of key topics such as Fault Modeling, Fault Simulation and Test Generation, Design for Testability (DFT), Scan-Based Testing, Test Diagnosis, and Memory Testing, which are critical components in modern chip design and validation. These sessions were meticulously designed to provide both theoretical understanding and practical insights into real-world testing challenges. The workshop also featured hands-on lab sessions using industry-standard VLSI testing tools, enabling participants to gain practical exposure and enhance their technical competencies. In addition to technical learning, the event provided valuable networking opportunities, allowing students to interact with experts and gain career guidance in the semiconductor industry. One of the core objectives of the workshop was to promote academic knowledge enhancement while fostering social awareness and outreach, encouraging students to apply their technical skills for societal advancement. Participants were also awarded certificates, recognizing their active involvement and successful completion of the program. Overall, the 3 Days TTTC India Workshop on VLSI Testing emerged as a highly impactful and knowledge-driven event, significantly contributing to skill development, industry readiness, and professional growth of the participants.
