Mamata Panigrahy
Mamata Panigrahy
Assistant Professor
Dr. Mamata Panigrahy currently works at School of Electronics Engineering, KIIT Bhubaneswar. She obtained her Doctorate degree from Electronics & Electrical Communication Engineering, Indian Institute of Technology Kharagpur. Mamata does research in Electronic Engineering, VLSI architectures designs for image processing applications.
Educational Qualification
PhD
Research Interests
VLSI ARCHITECTURE DESIGN ,DIGITAL SIGNAL PROCESSING,IMAGE PROCESSING ,BIO MEDICAL SIGNAL PROCESSING
Memberships
IAPQR ,ISTE
PhD
Research Interests
VLSI ARCHITECTURE DESIGN ,DIGITAL SIGNAL PROCESSING,IMAGE PROCESSING ,BIO MEDICAL SIGNAL PROCESSING
Memberships
IAPQR ,ISTE
Journals/Conferences :
1.M.Panigrahy, I.Chakrabarti, and A.S.Dhar, “Low-Delay Parallel Architecture for Fractal Image Compression”, Circuits, Systems and Signal Processing, March 2016, Vol-3, pp. 897-907.
2.M.Panigrahy, I.Chakrabarti, and A.S.Dhar, “Hardware Architecture for Fractal Image Encoder with Quadtree Partitioning", International Journal of Computer Application, ISBN 0975-8887, pp. 23-27.
3.Panigrahy M., Behera N.C., Vandana B., Chakrabarti I., Dhar A.S. (2017) Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder. In: Kaushik B., Dasgupta S., Singh V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore.
4.M.Panigrahy, I.Chakrabarti, and A.S. Dhar, “Hardware Implementation of Quadtree based Fractal Image Decoder", in Proceedings, 22nd National Conference on Communications: NCC2016, IEEE, IIT Guwahati, India, March 4-6, 2016,pp.1-6.
5.M.Panigrahy, I.Chakrabarti, and A.S.Dhar, “Hardware Architecture for Fractal Image Encoder with Quadtree Partitioning", in Proceedings, International Conference on Emerging Trends in Informatics and Communication (ICETIC), Brainware Group of Institutions, Kolkata, India, pp.131-136, Feb.20-21, 2016
6.M.Panigrahy, I.Chakrabarti, and A.S. Dhar, “ VLSI Design of Fast Fractal Image Encoder", in Proceedings, 18th International Symposium on VLSI Design and Test (VDAT), IEEE, Coimbatore, India, pp. 1-2, July 16-18, 2014.
7.M.Panigrahy, I.Chakrabarti, and A.S.Dhar, “Architecture for Fractal Image Encoder", in Proceedings, International Conference on VLSI and Signal Processing (ICVSP), IIT Kharagpur, India, Jan 10-12, 2014.
1.M.Panigrahy, I.Chakrabarti, and A.S.Dhar, “Low-Delay Parallel Architecture for Fractal Image Compression”, Circuits, Systems and Signal Processing, March 2016, Vol-3, pp. 897-907.
2.M.Panigrahy, I.Chakrabarti, and A.S.Dhar, “Hardware Architecture for Fractal Image Encoder with Quadtree Partitioning", International Journal of Computer Application, ISBN 0975-8887, pp. 23-27.
3.Panigrahy M., Behera N.C., Vandana B., Chakrabarti I., Dhar A.S. (2017) Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder. In: Kaushik B., Dasgupta S., Singh V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore.
4.M.Panigrahy, I.Chakrabarti, and A.S. Dhar, “Hardware Implementation of Quadtree based Fractal Image Decoder", in Proceedings, 22nd National Conference on Communications: NCC2016, IEEE, IIT Guwahati, India, March 4-6, 2016,pp.1-6.
5.M.Panigrahy, I.Chakrabarti, and A.S.Dhar, “Hardware Architecture for Fractal Image Encoder with Quadtree Partitioning", in Proceedings, International Conference on Emerging Trends in Informatics and Communication (ICETIC), Brainware Group of Institutions, Kolkata, India, pp.131-136, Feb.20-21, 2016
6.M.Panigrahy, I.Chakrabarti, and A.S. Dhar, “ VLSI Design of Fast Fractal Image Encoder", in Proceedings, 18th International Symposium on VLSI Design and Test (VDAT), IEEE, Coimbatore, India, pp. 1-2, July 16-18, 2014.
7.M.Panigrahy, I.Chakrabarti, and A.S.Dhar, “Architecture for Fractal Image Encoder", in Proceedings, International Conference on VLSI and Signal Processing (ICVSP), IIT Kharagpur, India, Jan 10-12, 2014.