About the faculty member
Biography and academic profile
Having 15 years of experience in the field of VLSI Design with a strong emphasis on: RTL design and verification. Design and implementation of FPGA-based prototypes for rapid prototyping and hardware acceleration. Experience with full-custom and standard cell design flows, including tape-out. Proficient in industry-standard EDA tools such as Synopsys, Cadence, and Mentor Graphics.
Academic and professional profiles
