Kananbala Ray
Kananbala Ray
Assistant Professor
She Received her M.Tech. degree in Electronics and Telecommunication Engineering from KIIT Deemed to be University ,Bhubaneswar, Odisha in 2006. She Received her Ph.D. degree in Electronics and Telecommunication Engineering from KIIT Deemed to be University ,Bhubaneswar, Odisha in 2017. She is currently working as Assistant Professor with the Department of School of Electronics Engineering since 1994. She has a total of 25 years of teaching experience in KIIT Deemed to be University. Her current research interests include Low power VLSI Memory Design and Image Compression.
Profile Links
Email :
[email protected]
Scopus Id :
57200819386
Google Scholar :
https://scholar.google.co.in/citations?user=owXeZE4AAAAJ&hl=en
Social Links
Research Interests
Low power VLSI Memory Design
Low power VLSI Memory Design
Journals/Conferences :
[1] K. B. Ray, S. K. Mandal and B. S. Patro, "Low Power High Speed Low Leakage Floating Gate SRAM Cell using Lector Technique“, Indian Journal of Science and Technology, vol.9, no.45, pp.1-6, Dec. 2016.
[2] K. B. Ray, S. K. Mandal and B. S. Patro, “Low Power FGSRAM Cell using Sleepy and Lector Technique“, Indonesian Journal of Electrical Engineering and Computer Science , vol. 4, no. 2, pp.333-340, Nov. 2016.
[3] K.B. Ray and B.S.Patro, "Leakage Power Minimization in ST-SRAM Cell Using Adaptive Reverse Body Bias Technique", International Journal of Computer Science and Mobile Applications, vol.6, no.4 , pp. 196-204, April- 2018 .
[4] K. B. Ray, N. Ghosh, B. Chowdhury and S. K. Mandal, "Low power 1 Bit SRAM Architecture Design Using GALEOR Technique", International Journal of Engineering Research & Technology(IJERT) Conference Proc. Special Issue , pp.44-49, 2016.
[5] B. Chowdhury, K. B. Ray, N. Ghosh and S. K. Mandal, '' Design and Analysis of Low Power, High Speed 3-2 Compressor Architectures in 45-nm Technology", International Journal of Engineering Research & Technology(IJERT), Conference Proc., Special issue, pp.24-28, 2016.
[6] P.P.Nanda, K.B.Ray and S.S.Das, "One Bit-Line Multi-Threshold SRAM Cell With High Read Stability", International Journal Of Innovative Research in Computer and Communication Engineering(IJIRCCE), vol.3, no.3,pp.1693-1697, March 2015.
[7] S.S.Das, K.B.Ray and P.P.Nanda, "Multi Threshold Low Power SRAM Using Floating Gates", International Journal Of Innovative Research in Computer and Communication Engineering(IJIRCCE), vol.3, no.3, pp.2370-2376, March 2015.
[8] A. Pattnaik and K. B. Ray " Leakage Power Minimization in Memory Design using an adaptive technique to optimize the Body Biasing Voltage“, International Journal of Scientific & Engineering Research, vol.5, no.3, pp.1253-1261, Mar. 2014.
[9] K.B.Ray and B. S. Patro, "Low Power High Stability SRAM Cell with Combined Effect of Sleepy-Stack and Diode Gated Technique", International Conference on Applied Electromagnetics, Signal Processing and Communication(AESPC), IEEE, 22nd-24th, Oct 2018.
[10] B. Senapati, G. L. Kumar M and K. B. Ray, "High Resolution Reconfigurable Biopotential Processor for Portable Biomedical Application”, 2nd International Conference on Devices for Integrated Circuit (DevIC), IEEE EDS, pp.517-521, Mar. 2017.
[11] K. B. Ray and S. K. Mandal, "Low Power SRAM Design", Participated in the poster competition held during "National Science Day" celebration, KIIT University, Bhubaneswar, Feb. 2014.
[12] K. B. Ray , S. S. Das, and S. K. Mandal, "Low Power FGSRAM " Participated in the Poster Presentation in IEEE EDS Bhubaneswar Kolkata Mini-Colloquium on 'Advanced Electronic Devices and Circuits' jointly organized by IEEE EDS Calcutta Chapter, ED University of Calcutta Student Branch chapter, ED Heritage Institute of Technology Student Branch Chapter and School of Electronics Engineering, KIIT University, Dec. 2014.
[13] K. B. Ray, P. P. Panda, and S. K. Mandal, "Low Power Single Bit-Line SRAM Design" Participated in the Poster Presentation in IEEE EDS Bhubaneswar Kolkata Mini-Colloquium on 'Advanced Electronic Devices and Circuits' jointly organized by IEEE EDS Calcutta Chapter, ED University of Calcutta Student Branch chapter, ED Heritage Institute of Technology Student Branch Chapter and School of Electronics Engineering, KIIT University, Dec. 2014.
[1] K. B. Ray, S. K. Mandal and B. S. Patro, "Low Power High Speed Low Leakage Floating Gate SRAM Cell using Lector Technique“, Indian Journal of Science and Technology, vol.9, no.45, pp.1-6, Dec. 2016.
[2] K. B. Ray, S. K. Mandal and B. S. Patro, “Low Power FGSRAM Cell using Sleepy and Lector Technique“, Indonesian Journal of Electrical Engineering and Computer Science , vol. 4, no. 2, pp.333-340, Nov. 2016.
[3] K.B. Ray and B.S.Patro, "Leakage Power Minimization in ST-SRAM Cell Using Adaptive Reverse Body Bias Technique", International Journal of Computer Science and Mobile Applications, vol.6, no.4 , pp. 196-204, April- 2018 .
[4] K. B. Ray, N. Ghosh, B. Chowdhury and S. K. Mandal, "Low power 1 Bit SRAM Architecture Design Using GALEOR Technique", International Journal of Engineering Research & Technology(IJERT) Conference Proc. Special Issue , pp.44-49, 2016.
[5] B. Chowdhury, K. B. Ray, N. Ghosh and S. K. Mandal, '' Design and Analysis of Low Power, High Speed 3-2 Compressor Architectures in 45-nm Technology", International Journal of Engineering Research & Technology(IJERT), Conference Proc., Special issue, pp.24-28, 2016.
[6] P.P.Nanda, K.B.Ray and S.S.Das, "One Bit-Line Multi-Threshold SRAM Cell With High Read Stability", International Journal Of Innovative Research in Computer and Communication Engineering(IJIRCCE), vol.3, no.3,pp.1693-1697, March 2015.
[7] S.S.Das, K.B.Ray and P.P.Nanda, "Multi Threshold Low Power SRAM Using Floating Gates", International Journal Of Innovative Research in Computer and Communication Engineering(IJIRCCE), vol.3, no.3, pp.2370-2376, March 2015.
[8] A. Pattnaik and K. B. Ray " Leakage Power Minimization in Memory Design using an adaptive technique to optimize the Body Biasing Voltage“, International Journal of Scientific & Engineering Research, vol.5, no.3, pp.1253-1261, Mar. 2014.
[9] K.B.Ray and B. S. Patro, "Low Power High Stability SRAM Cell with Combined Effect of Sleepy-Stack and Diode Gated Technique", International Conference on Applied Electromagnetics, Signal Processing and Communication(AESPC), IEEE, 22nd-24th, Oct 2018.
[10] B. Senapati, G. L. Kumar M and K. B. Ray, "High Resolution Reconfigurable Biopotential Processor for Portable Biomedical Application”, 2nd International Conference on Devices for Integrated Circuit (DevIC), IEEE EDS, pp.517-521, Mar. 2017.
[11] K. B. Ray and S. K. Mandal, "Low Power SRAM Design", Participated in the poster competition held during "National Science Day" celebration, KIIT University, Bhubaneswar, Feb. 2014.
[12] K. B. Ray , S. S. Das, and S. K. Mandal, "Low Power FGSRAM " Participated in the Poster Presentation in IEEE EDS Bhubaneswar Kolkata Mini-Colloquium on 'Advanced Electronic Devices and Circuits' jointly organized by IEEE EDS Calcutta Chapter, ED University of Calcutta Student Branch chapter, ED Heritage Institute of Technology Student Branch Chapter and School of Electronics Engineering, KIIT University, Dec. 2014.
[13] K. B. Ray, P. P. Panda, and S. K. Mandal, "Low Power Single Bit-Line SRAM Design" Participated in the Poster Presentation in IEEE EDS Bhubaneswar Kolkata Mini-Colloquium on 'Advanced Electronic Devices and Circuits' jointly organized by IEEE EDS Calcutta Chapter, ED University of Calcutta Student Branch chapter, ED Heritage Institute of Technology Student Branch Chapter and School of Electronics Engineering, KIIT University, Dec. 2014.